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page : 1 rev. 0.09a : 2011.09.14 rev. 0.09a 2011.09.14 r1qba36**cb* / r1qea36**cb* series features ? power supply ? 1.8 v for core (v dd ), 1.4 v to v dd for i/o (v ddq ) ? clock ? fast clock cycle time for high bandwidth ? two input clocks (k and /k) for precise ddr timing at clock rising edges only ? two output echo clocks (cq and /cq) simplify data capture in high-speed systems ? clock-stop capability with p s restart ? i/o ? common data input/output bus ? pipelined double data rate operation ? hstl i/o ? user programmable output impedance ? dll/pll circuitry for wide output data valid wi ndow and future frequency scaling ? data valid pin (qvld) to indicate valid data on the output ? function ? two-tick burst for low ddr transaction size ? internally self-timed write control ? simple control logic for easy depth expansion ? jtag 1149.1 compatible test access port ? package ? 165 fbga package (15 x 17 x 1.4 mm) description the r1q # a3636 is a 1,048,576-word by 36-bit and the r1q # a3618 is a 2,097,152-word by 18-bit synchronous double data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. it integrates unique synchronous pe ripheral circuitry and a burst counter. all input registers are controlled by an input clock pair (k and /k) and are latched on the positive edge of k and /k. these products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these products are packaged in 165-pin plastic fbga package. # = b: latency =2.5, w/o odt # = h: latency =2.0, w/o odt # = e: latency =2.5, w/ odt # = l: latency =2.0, w/ odt 36-mbit ddrii+ sram 2-word burst r1qba3636cbg / r1qba3618cbg / r1qba3609cbg r1qea3636cbg / r1qea3618cbg / r1qea3609cbg r1qha3636cbg / r1qha3618cbg / r1qha3609cbg r1qla3636cbg / r1qla3618cbg / r1qla3609cbg notes: 1. qdr rams and quad data rate rams comprise a new fam ily of products devel oped by cypress semiconductor, idt, samsung, and renesas electronics corp. (qdr co-development team) 2. the specifications of this device are subject to ch ange without notice. please contact your nearest renesas electronics sales office regarding specifications. 3. refer to " http://www.renesas.com/products/memory/fast_sram/qdr_sram/qdr_sram_root.jsp " for the latest and detailed information. 4. descriptions about x9 parts in this datasheet are just for reference. r10ds0159ej0009 r10ds0159ej0009
page : 2 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series part number definition common 0q %qoogpvu 0q %qoogpvu 0q %qoogpvu 4 4gpgucu/goqt[2tghkz # 8ff8 (tgswgpe[/*\ 3 3&4++$ =?
. =? &gpukv[/d (tgswgpe[/*\ 3 3&4++$
. &gpukv[/d (tgswgpe[/ *\ 3 &&4++$
. &gpukv[/d (tgswgpe[/ *\ 3 &&4++$
. &gpukv[/d (tgswgpe[/ *\ 3 &&4++$5+1 =?
. &cvcykfvjdkv (tgswgpe[/*\ 3# 3&4++ $. =? &cvcykfvjdkv (tgswgpe[/*\ 3$ &&4++ $. &cvcykfvjdkv (tgswgpe[/*\ 3% &&4++ $. 4 uv)gpgtcvkqp (tgswgpe[/*\ 3& 3&4++ $.y1&6 =? # pf)gpgtcvkqp (tgswgpe[/*\ 3' &&4++ $.y1&6 $ tf)gpgtcvkqp (tgswgpe[/*\ 3( &&4++ $.y1&6 % vj)gpgtcvkqp 3) 3&4++ $. & vj)gpgtcvkqp 3* &&4++ $. ' vj)gpgtcvkqp 3, &&4++ $. ( vj)gpgtcvkqp 3- 3&4++ $.y1&6 $) 2-)$)#zoo # 2d htgg cpf6tc[ 3. &&4++ $.y1&6 $# 2-)$)#zoo $ 2dhtggcpf6tc[ 3/ &&4++ $.y1&6 6 2d htgg cpf6crg4ggn 30 3&4++ $. 5 2dhtggcpf6crg4ggn 32 3&4++ $.y1&6 0qvg =?$$wtuvngpivj
$$wtuvngpivj$$wtuvngpiv j =?.4gcf.cvgpe[
.4gcf.cvgpe[e[eng.e [eng.e[eng =?5+15grctcvg+1 =?1&61pfkgvgtokpcvkqp 0qvg 2cemcig/ctmkpi0cog 2d htgg rctvu/ctmkpi0cog2ctv0wodgt
2dhtggrctvu/ctmkpi0cog2ctv0wodgt
2$(
'zcorng43##4$)4 2d( 2d htgg rctvu
'zcorng 43##4$)42$(2dhtggrctvu 0qvg 2d htgg 4q*5%qornkcpeg.gxgn 2dhtgg4q*5%qornkcpeg.gxgn `#`< qt0qpg 4gpgucukpvgtpcnwug 4 + %qoogtekcnvgor 6ctcpig? +pfwuvtkcnvgor 6ctcpig? part number definition table 0 b r 0 2 - g b r 6 3 4 4 a a q 1 r example 16 15 14 13 12 - 11 10 9 8 7 6 5 4 3 2 1 0 no. r10ds0159ej0009
page : 3 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 00000.0000.0000.0000.0000 -- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000--- 036m 533 500 450 400 375 333 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-30-33-40-50 17 x18 r1q a a36 18 c b v - yy 18 x36 r1q a a36 36 c b v - yy 20 x18 r1q b a36 18 c b v - yy 21 x36 r1q b a36 36 c b v - yy 23 x18 r1q c a36 18 c b v - yy 24 x36 r1q c a36 36 c b v - yy 26 x18 r1q d a36 18 c b v - yy 27 x36 r1q d a36 36 c b v - yy 29 x18 r1q e a36 18 c b v - yy 30 x36 r1q e a36 36 c b v - yy 32 x18 r1q f a36 18 c b v - yy 33 x36 r1q f a36 36 c b v - yy 35 x18 r1q g a36 18 c b v - yy 36 x36 r1q g a36 36 c b v - yy 38 x18 r1q h a36 18 c b v - yy 39 x36 r1q h a36 36 c b v - yy 41 x18 r1q j a36 18 c b v - yy 42 x36 r1q j a36 36 c b v - yy 44 x18 r1q k a36 18 c b v - yy 45 x36 r1q k a36 36 c b v - yy 47 x18 r1q l a36 18 c b v - yy 48 x36 r1q l a36 36 c b v - yy 50 x18 r1q m a36 18 c b v - yy 51 x36 r1q m a36 36 c b v - yy -25 -25 -25 -25 -25 -25 -20 -20 -22 -22 organi- zation -20 -20 -20 -20 no product type burst length latency (cycle) 2.0 b4 ddrii+ qdrii+ b4 ddrii+ b2 b4 qdrii+ b4 qdrii+ b4 2.0 ddrii+ b2 b4 yes b4 b2 ddrii+ b4 qdrii+ -19 -19 2.5 2.5 b2 -19 -19 -19 -19 -22 -22 -22 -22 frequency (max) (mhz) cycle time (min) (ns) no yes no odt part number qdr ii+ / ddr ii+ qdr ii / ddr ii notes: 1. " yy " represents the speed bin . "r1qaa3636cbg- 20 " can operate at 500 mhz(max) of frequency, for example. 2. " v " represents the package size . if " v " = " g " then size is 15 x 17 mm, and if " v " = " a " then 13 x 15 mm. 3. the part which is not listed above is not supported, as of the day when this datasheet was issued, in spite of the existence of the part number or datasheet. 36m qdr ii+ / ddr ii+ sram lineup - renesas supports or plans to su pport the parts listed below. r10ds0159ej0009
page : 4 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series r1q4a3618 (top) / r1qb(h)a3618 (mid) / r1qe(l)a3618 (bottom) 11 10 9 8 7 6 5 4 3 2 1 (top view) notes: 1. address expansion order for future higher density srams: 10a z 2a z 7a z 5b. 2. nc pins can be left floating or connected to 0v : v ddq . tdi dq0 nc nc dq2 dq3 nc zq nc dq5 dq6 nc nc dq8 cq tms nc nc dq1 nc nc dq4 v ref nc nc nc nc dq7 nc sa sa nc nc nc nc nc nc v ddq nc nc nc nc nc nc sa sa sa v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss sa /ld sa sa sa v ss v ss v dd v dd v dd v dd v dd v ss v ss sa /bw0 nc /c nc odt c qvld qvld sa v ss v ss v ss v ss v ss v ss v ss v ss v ss sa0 nc nc k /k sa sa sa v ss v ss v dd v dd v dd v dd v dd v ss v ss sa nc /bw1 sa sa v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss sa r-/w sa dq17 dq16 nc nc dq14 nc v ddq dq13 nc dq11 dq10 nc nc sa tck nc nc nc dq15 nc nc v ref nc dq12 nc nc nc dq9 nc tdo nc nc nc nc nc nc /doff nc nc nc nc nc nc /cq r p n m l k j h g f e d c b a r1q4a3636 (top) / r1qb(h)a3636 (mid) / r1qe(l)a3636 (bottom) 11 10 9 8 7 6 5 4 3 2 1 (top view) notes: 1. address expansion order for future higher density srams: 10a z 2a z 7a z 5b. 2. nc pins can be left floating or connected to 0v : v ddq . tdi dq0 dq10 dq1 dq2 dq3 dq4 zq dq14 dq5 dq6 dq16 dq7 dq8 cq tms dq9 nc dq11 nc dq12 dq13 v ref nc nc dq15 nc dq17 nc nc sa nc nc nc nc nc nc v ddq nc nc nc nc nc nc sa sa sa v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss sa /ld sa sa sa v ss v ss v dd v dd v dd v dd v dd v ss v ss sa /bw0 /bw1 /c nc odt c qvld qvld sa v ss v ss v ss v ss v ss v ss v ss v ss v ss sa0 nc nc k /k sa sa sa v ss v ss v dd v dd v dd v dd v dd v ss v ss sa /bw3 /bw2 sa sa v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss sa r-/w sa dq26 dq25 dq34 dq24 dq23 dq32 v ddq dq22 dq21 dq20 dq19 dq28 dq18 sa tck nc dq35 nc dq33 nc nc v ref dq31 dq30 nc dq29 nc dq27 nc tdo nc nc nc nc nc nc /doff nc nc nc nc nc nc /cq r p n m l k j h g f e d c b a pin arrangement top x r1q4a3636 mid x r1qb(h)a3636 bottom x r1qe(l)a3636 r10ds0159ej0009
page : 5 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series r1q4a3609 (top) / r1qb(h)a3609 (mid) / r1qe(l)a3609 (bottom) 11 10 9 8 7 6 5 4 3 2 1 (top view) notes: 1. address expansion order for future higher density srams: 10a z 2a z 7a z 5b. 2. nc pins can be left floating or connected to 0v : v ddq . 3. note that 6c is not sa0 and 7c is not sa1 in x9 product. thus u 9 product does not permit random start address on the two least significant address bits. sa0, sa1 = 0 at the start of each address. tdi dq0 nc nc dq1 nc nc zq nc nc dq3 nc nc dq4 cq tms nc nc nc nc nc dq2 v ref nc nc nc nc nc nc sa sa nc nc nc nc nc nc v ddq nc nc nc nc nc nc sa sa sa v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss sa /ld sa sa sa v ss v ss v dd v dd v dd v dd v dd v ss v ss sa /bw nc /c nc odt c qvld qvld sa v ss v ss v ss v ss v ss v ss v ss v ss v ss sa k /k sa sa sa v ss v ss v dd v dd v dd v dd v dd v ss v ss sa nc nc sa sa v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss sa r-/w sa dq8 nc nc nc nc nc v ddq dq6 nc dq5 nc nc nc sa tck nc nc nc dq7 nc nc v ref nc nc nc nc nc nc nc tdo nc nc nc nc nc nc /doff nc nc nc nc nc nc /cq r p n m l k j h g f e d c b a pin arrangement just reference r10ds0159ej0009
page : 6 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series notes: 1. r1q2, r1q3, r1q4, r1q5, r1q6 series have c and /c pins. r1qa, r1qb, r1qc, r1qd, r1qe, r1qf, r1qg, r1qh, r1qj, r1qk, r1ql, r1qm, r1qn, r1qp series do not have c, /c pins. in the series, k and /k are used as the output reference clocks instead of c and /c. therefore, hereafter, c and /c represent k and /k in this document. pin descriptions 1 notes ieee1149.1 clock input: 1.8 v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. input tck ieee1149.1 test inputs: 1.8 v i/o levels. these balls may be left not connected if the jtag function is not used in the circuit. input tms tdi dll/pll disable: when low, this input causes the dll/pll to be bypassed for stable, low frequency operation. input /doff output clock: this clock pair provides a user-controlled means of tuning device output data. the rising edge of /c is used as the output timing reference for the first and third output data. the rising edge of c is used as the output timing reference for second and fourth output data. ideally, /c is 180 degrees out of phase with c. c and /c may be tied high to force the use of k and /k as the output reference clocks instead of having to provide c and /c clocks. if tied high, c and /c must remain high and not to be toggled during device operation. these balls cannot remain v ref level. input c, /c (ii only) input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of /k. /k is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. these balls cannot remain v ref level. input k, /k synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of k and /k for each of the two rising edges comprising the write cycle. see byte write truth table for signal to data relationship. input /bw x synchronous read / write input: when /ld is low, this input designates the access type (read when r-/w is high, write when r-/w is low) for the loaded address. r-/w must meet the setup and hold times around the rising edge of k. input r-/w synchronous load: this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read / write direction. all transactions operate on a burst-of-four data (two clock periods of bus activity). input /ld synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of k. all transactions operate on a burst-of-four words (two clock periods of bus activity). sa0 and sa1 are used as the lowest two address bits for burst read and burst write operations permitting a random burst start address on u 18 and u 36 of ddr ii (not ii+) devices. these inputs are ignored when device is deselected or once burst operation is in progress. input sa x descriptions i/o type name hins=00111.0011.0011.0011.0011 ---00111.0011.0011.0011.0011--- 00111.0011.0011.0011.0011 ---ddr r10ds0159ej0009
page : 7 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series 1 odt control: when low ; [option 1] low range mode is selected. the impedance range is between 52 : and 105 : (thevenin equivalent), which follows 0.3 u rq for 175 : 7 rq 7 350 : . [option 2] odt is disabled. when high ; high range mode is selected. the impedance range is between 105 : and 150 : (thevenin equivalent), which follows 0.6 u rq for 175 : 7 rq 7 250 : . when floating ; [option 1] high range mode is selected. [option 2] odt is disabled. input odt (ii+ only) output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. dq and cq output impedance are set to 0.2 u rq, where rq is a resistor from this ball to ground. this ball can be connected directly to v ddq , which enables the minimum impedance mode. this ball cannot be connected directly to v ss or left unconnected. in odt (on die termination) enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. input zq valid output indicator: the q valid indicates valid output data. qvld is edge aligned with cq and /cq. output qvld (ii+ only) no connect: these pins can be left floating or connected to 0v : v ddq . nc notes: 1. renesas status: option 1 = available, option 2 = possible. 2. all power supply and ground balls must be connected for proper operation of the device. 2 2 2 notes hstl input reference voltage: nominally v ddq /2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffers. v ref power supply: ground. supply v ss power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operating conditions for range. supply v ddq power supply: 1.8 v nominal. see dc characteristics and operating conditions for range. supply v dd ieee 1149.1 test output: 1.8 v i/o level. output tdo synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when dq tri- states. output cq, /cq synchronous data i/os: input data must meet setup and hold times around the rising edges of k and /k. output data is synchronized to the respective c and /c, or to the respective k and /k if c and /c are tied high. the u 9 device uses dq0 ~ dq8. dq9 ~ dq35 should be treated as nc pin. the u 18 device uses dq0 ~ dq17. dq18 ~ dq35 should be treated as nc pin. the u 36 device uses dq0 ~ dq35. input / output dq 0 to dq n descriptions i/o type name r10ds0159ej0009
page : 8 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series block diagram (r1qxa3636 / r1qxa3618 series, x=4) /ld /bwx k /k 72 /36 72 /36 20/21 36/18 36/18 dq 20/21 k c,/c or k,/k zq 2 cq, /cq 72 /36 4/2 r-/w sa0 sa0' memory array write register output register output select output buffer write driver sense amp mux burst logic output control logic sa0'' sa0''' sa /ld r-/w k address registry and logic data registry and logic /k notes 1. c and /c pins do not exist in ii+ series parts. c or k block diagram (r1qxa3636 / r1qxa3618 / r1qya3609 series, x=b,e,h,l, y=4,b,e,h,l) /ld /bwx k /k 72 /36 /18 19/20/21 36/18/9 36/18/9 dq 19/20/21 k c,/c or k,/k zq 2 cq, /cq memory array write register output register output select output buffer write driver sense amp mux 4/2/1 r-/w 72 /36 /18 72 /36 /18 sa /ld r-/w k address registry and logic data registry and logic /k notes 1. c and /c pins do not exist in ii+ series parts. c or k r10ds0159ej0009
page : 9 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 ---00000.0000.0000.0000.0000 --- 72m_36m status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff 2. double clock mode k, /k fix high (=vddq) c, /c status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff 1. single clock mode (c and /c pins fixed high) k, /k fix high (=vddq) general description power-up and initialization sequence -v dd must be stable before k, /k clocks are applied. - recommended voltage app lication sequence : v ss z v dd z v ddq & v ref z v in . (0 v to v dd , v ddq < 200 ms) -apply v ref after v ddq or at the same time as v ddq . - then execute either one of the following three sequences. 1. single clock mode (c and /c tied high) - drive /doff high (/doff can be tied high from the start). - then provide stable clocks (k, /k) for at least 1024 cycles (ii series) or 20 us (ii+ series). these meet the qdr common specification of 20 us. when the operating frequency is less than 180 mhz, 2048 cycles are required (ii series). 2. double clock mode (c and /c control outputs) ( ii series only ) - drive /doff high (/doff can be tied high from the start) - then provide stable clocks (k, /k , c, /c) for at least 1024 cycles (ii series). this meets the qdr common specification of 20 us. when the operating frequency is less than 180 mhz, 2048 cycles are required (ii series). 3. dll/pll off mode (/doff tied low) - in the "nop and setup stage", provide stable clocks (k, /k) for at least 1024 cycles (ii series) or 20 us (ii+ series). these meet the qdr common specification of 20 us. r10ds0159ej0009
page : 10 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series common dll/pll constraints 1. dll/pll uses k clock as its synchronizing input. the input should have low phase jitter which is specified as tkc var. 2. the lower end of the frequency at which the dll/pll can operate is 120 mhz. (please refer to ac characteristics table for detail.) 3. when the operating frequency is changed or /doff level is changed, setup cycles are required again. programmable output impedance 1. output buffer impedance can be programmed by termi nating the zq ball to v ss through a precision resistor (rq). the value of rq is five times the output im pedance desired. the allowa ble range of rq to guarantee impedance matching with a tolerance of 15% is 250 : typical. the total external capacitance of zq ball must be less than 7.5 pf. r10ds0159ej0009
page : 11 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series iip qvld (valid data indicator) (r1qa, r1qb, r1qc, r1qd, r1qe, r1qf, r1qg, r1qh, r1qj, r1qk, r1ql, r1qm r1qn, r1qp series) 1. qvld is provided on the qdr-ii+ and ddr-ii+ to simplify data capture on high speed systems. the q valid indicates valid output data. qvld is activated half cycle before the read data for the receiver to be ready for capturing the data. qvld is inactivated half cycle before the read finish for the receiver to stop capturing the data. qvld is edge aligned with cq and /cq. 6 - 3 : (odt disable) 0.6 u rq floating 2, 5 : 0.6 u rq 0.6 u rq high thevenin equivalent resistance (r thev ) : unit odt range (odt disable) option 2 notes: 1. allowable range of rq for option 1 to guarantee impedance matching a tolerance of r 20 % is 175 : 7 rq 7 350 : . 2. allowable range of rq to guarantee impedance matching a tolerance of r 20 % is 175 : 7 rq 7 250 : . 3. allowable range of rq for option 1 to guarantee impedance matching a tolerance of r 20 % is 175 : 7 rq 7 250 : . 4. at option 1, odt control pin is connected to v ddq through 3.5 k : . therefore it is recommended to connect it to v ss through less than 100 : to make it low. 5. at option 2, odt control pin is connected to v ss through 3.5 k : . therefore it is recommended to connect it to v ddq through less than 100 : to make it high. 6. renesas status: option 1 = available, option 2 = possible. if you need devices with option 2, please contact renesas sales office. 1, 4 0.3 u rq low notes option 1 odt control pin odt (on die termination) (r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series) 1. to reduce reflection which produ ces noise and lowers signal qualit y, the signals should be terminated, especially at high frequency. renesas offers odt on the in put signals to qdr-ii+ and ddr-ii+ family of devices. (see the odt pin table) 2. in odt enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. (see the odt range table) 3. in ddr-ii+ devices having common i/o bus, odt is automatically enabled when the device inputs data and disabled when the device outputs data. 4. there is no difference in ac timing characteristics between the srams with odt and srams without odt. 5. there is no increase in the i dd of srams with odt, however, there is an increase in the i ddq (current consumption from the i/o voltage supply) with odt. r10ds0159ej0009
page : 12 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series iip thevenin termination output buffer sram with odt 2 u r thev 2 u r thev v ddq other lsi input buffer v ss zq v ss rq odt pin = low or floating odt pin = high off: first read command + read latency - 0.5 cycle on: last read command + read latency + bl/2 cycle + 0.5 cycle (see below timing chart) 3 2 always off dq 0 ~dq n in common i/o devices always off always on k, /k always off always on /bw x always off odt on/off timing odt pin (r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series) option 2 notes: 1. separate i/o devices are r1qd, r1qk, r1qp series. 2. common i/o devices are r1qe, r1qf, r1ql, r1qm series. 3. renesas status: option 1 = available, option 2 = possible. if you need devices with option 2, please contact renesas sales office. 1 always on d 0 ~d n in separate i/o devices notes option 1 pin name r10ds0159ej0009
page : 13 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series iip nop command read (b2) ra k, /k status qa qb qb rc qc qc qd qd nop nop nop write (b2) we de de df df dg dg dh dh wg write (b2) qa dq dq odt disabled qj qi ri qi read (b2) enabled disabled enabled odt on/off timing chart for r1qe series (ddr ii+, burst length=2, read latency=2.5 cycle) read (b2) read (b2) read (b2) rb rd wf wh rj read (b2) write (b2) write (b2) nop command read (b4) ra k, /k status qa qa qa rc qc qc qc qc nop nop nop write (b4) we de de de de dg dg dg dg wg write (b4) qa dq dq odt disabled qi qi ri qi read (b4) enabled disabled enabled odt on/off timing chart for r1qf series (ddr ii+, bu rst length=4, read latency=2.5 cycle) - read (b4) - - - - nop command read (b2) ra k, /k status qa qb qb rc qc qc qd qd nop nop write (b2) we de de df df dg dg dh dh wg write (b2) qa dq dq odt disabled qj qi ri qi read (b2) enabled disabled enabled odt on/off timing chart for r1ql series (ddr ii+, burst length=2, read latency=2.0 cycle) read (b2) read (b2) read (b2) rb rd wf wh rj read (b2) write (b2) write (b2) qj read (b2) rk qk qk nop command read (b4) ra k, /k status qa qa qa rc qc qc qc qc nop nop write (b4) we de de de de dg dg dg dg wg write (b4) qa dq dq odt disabled qi qi ri qi read (b4) enabled disabled enabled odt on/off timing chart for r1qm series (ddr ii+, bu rst length=4, read latency=2.0 cycle) - read (b4) - - - - qi read (b4) rk qk qk notes 1. odt on/off switching timings ar e edge aligned with cq or /cq. r10ds0159ej0009
page : 14 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series c(t+3) y /c(t+2) y rl=2.5 /c(t+2) y c(t+2) y rl=2.0 rl *8 =1.5 q(a2) q(a1) output data d(a2) d(a1) input data c(t+2) y /c(t+1) y input clock for q /k(t+1) y k(t+1) y input clock data out data in standby (clock stopped) nop (no operation) read cycle: load address, output read data on consecutive c and /c rising edges write cycle: load address, input write data on consecutive k and /k rising edges operation k truth table notes: 1. h: high level, l: low level, u : don?t care, y : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at c and /c rising edges, except if c and /c are high, then data outputs are delivered at k and /k rising edges. 3. /ld and r-/w must meet setup/hold times around the rising edges (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that will en sure the outputs will be in high-z during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. when clocks are stopped, the following cases are recommended; the case of k = low, /k = high, c = low and /c = high, or the case of k = high, /k = low, c = high and /c = low. this condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. a1 refers to the address input during a write or read cycle. a2 refers to the next internal burst address in accordance with the linear burst sequence. 8. rl = read latency (unit = cycle). h l y high-z u h y previous state u u stopped l l y dq r-/w /ld k notes sa0 sa0 0 1 1st internal burst address external address burst sequence linear burst sequence table (r1q4aww36 / r1q4aww18 series ) 1 0 r10ds0159ej0009
page : 15 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series write nothing write d27 to d35 write d18 to d26 write d9 to d17 write d0 to d8 write d0 to d35 operation h h h h - y h h h h y - l h h h - y l h h h y - h l h h - y h l h h y - h h l h - y h h l h y - h h h l - y h h h l y - /bw3 /bw1 byte write truth table ( x 36 ) notes: 1. h: high level, l: low level, y : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. l l l l y - l l l l - y /bw2 /bw0 /k k common write nothing write d9 to d17 write d0 to d8 write d0 to d17 operation h h - y h h y - l h - y l h y - h l - y h l y - byte write truth table ( x 18 ) notes: 1. h: high level, l: low level, y : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. l l y - l l - y /bw1 /bw0 /k k write nothing write d0 to d8 operation h - y h y - byte write truth table ( x 9 ) notes: 1. h: high level, l: low level, y : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. l y - l - y /bw /k k just reference except r1q2a7209 series r10ds0159ej0009
page : 16 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series notes: 1. sa0 is internally advanced in accordance with the burst order table. bus cycle is terminated at the end of this sequence (burst count = 2). 2. state machine control timing sequence is controlled by k. bus cycle state diagram nop write double count = count + 2 load new address count = 0 power up /ld = h supply voltage provided /ld = l r-/w = l /ld = l & count = 2 /ld = h & count = 2 read double count = count + 2 r-/w = h /ld = l & count = 2 /ld = h & count = 2 r10ds0159ej0009
page : 17 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series absolute maximum ratings notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.5 v, whatever the instantaneous value of v ddq . 5. some method of cooling or airflow should be considered in the system. (especially for high frequency or odt parts) q c q c v v v v unit 1, 4 0.5 to v ddq + 0.5 (2.5 v max.) v i/o input/output voltage 1, 4 0.5 to 2.5 v dd core supply voltage 1, 4 0.5 to v dd v ddq output supply voltage 5 +125 (max) tj junction temperature 55 to +125 t stg storage temperature 1, 4 0.5 to v dd + 0.5 (2.5 v max.) v in input voltage on any ball notes rating symbol parameter common recommended dc operating conditions 0.75 1.5 1.8 typ v ref 0.1 v ddq + 0.3 0.95 v dd 1.9 max notes: 1. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . 2. please pay attention to tj not to exceed the temperature shown in the absolute maximum ratings table due to current from v ddq . 3. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 4. these are dc test criteria. the ac v ih / v il levels are defined separately to measure timing parameters. 5. overshoot: v ih (ac) d v ddq + 0.5 v for t d t khkh /2 undershoot: v il (ac) t 0.5 v for t d t khkh /2 during normal operation, v ih(dc) must not exceed v ddq and v il(dc) must not be lower than v ss . v v v v v unit 1, 2 1.4 v ddq power supply voltage -- i/o 3 0.68 v ref input reference voltage -- i/o 1, 4, 5 v ref + 0.1 v ih (dc) input high voltage 1, 4, 5 0.3 v il (dc) input low voltage 1 1.7 v dd power supply voltage -- core notes min symbol parameter r10ds0159ej0009
page : 18 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 00000.0000.0000.0000.0000 -- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000--- 036m dc characteristics (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series, ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v, v ddq = 1.5v, v ref = 0.75v) operating supply current (write / read) symbol = i dd . unit = ma. see notes 1, 2 and 3 in the page after next. notes: 1. " yy " represents the speed bin . "r1qaa3636cbg- 20 " can operate at 500 mhz(max) of frequency, for example. 2. " v " represents the package size . if " v " = " g " then size is 15 x 17 mm, and if " v " = " a " then 13 x 15 mm. 533 500 450 400 375 333 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-30-33-40-50 17 x18 r1q a a36 18 c b v - yy 1220 1160 1070 18 x36 r1q a a36 36 c b v - yy 1280 1220 1130 20 x18 r1q b a36 18 c b v - yy 1030 990 920 21 x36 r1q b a36 36 c b v - yy 1110 1060 990 23 x18 r1q c a36 18 c b v - yy 820 790 750 24 x36 r1q c a36 36 c b v - yy 880 850 800 26 x18 r1q d a36 18 c b v - yy 1220 1160 1070 27 x36 r1q d a36 36 c b v - yy 1280 1220 1130 29 x18 r1q e a36 18 c b v - yy 1030 990 920 30 x36 r1q e a36 36 c b v - yy 1110 1060 990 32 x18 r1q f a36 18 c b v - yy 820 790 750 33 x36 r1q f a36 36 c b v - yy 880 850 800 35 x18 r1q g a36 18 c b v - yy 1070 980 36 x36 r1q g a36 36 c b v - yy 1150 1060 38 x18 r1q h a36 18 c b v - yy 920 850 39 x36 r1q h a36 36 c b v - yy 990 910 41 x18 r1q j a36 18 c b v - yy 750 710 42 x36 r1q j a36 36 c b v - yy 800 760 44 x18 r1q k a36 18 c b v - yy 1070 980 45 x36 r1q k a36 36 c b v - yy 1150 1060 47 x18 r1q l a36 18 c b v - yy 920 850 48 x36 r1q l a36 36 c b v - yy 990 910 50 x18 r1q m a36 18 c b v - yy 750 710 51 x36 r1q m a36 36 c b v - yy 800 760 qdr ii+ / ddr ii+ qdr ii / ddr ii frequency (max) (mhz) cycle time (min) (ns) no yes no odt part number organi- zation 2.5 2.5 b2 yes b4 b2 ddrii+ b4 qdrii+ qdrii+ b4 2.0 ddrii+ b2 b4 2.0 b4 ddrii+ qdrii+ b4 ddrii+ b2 b4 qdrii+ b4 no product type burst length latency (cycle) r10ds0159ej0009
page : 19 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 00000.0000.0000.0000.0000 -- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000--- 036m standby supply current (nop) symbol = i sb1 . unit = ma. see notes 2, 4 and 5 in the next page. notes: 1. " yy " represents the speed bin . "r1qaa3636cbg- 20 " can operate at 500 mhz(max) of frequency, for example. 2. " v " represents the package size . if " v " = " g " then size is 15 x 17 mm, and if " v " = " a " then 13 x 15 mm. 533 500 450 400 375 333 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-30-33-40-50 17 x18 r1q a a36 18 c b v - yy 870 830 780 18 x36 r1q a a36 36 c b v - yy 910 870 810 20 x18 r1q b a36 18 c b v - yy 870 840 780 21 x36 r1q b a36 36 c b v - yy 960 920 860 23 x18 r1q c a36 18 c b v - yy 690 660 630 24 x36 r1q c a36 36 c b v - yy 730 710 670 26 x18 r1q d a36 18 c b v - yy 870 830 780 27 x36 r1q d a36 36 c b v - yy 910 870 810 29 x18 r1q e a36 18 c b v - yy 870 840 780 30 x36 r1q e a36 36 c b v - yy 960 920 860 32 x18 r1q f a36 18 c b v - yy 690 660 630 33 x36 r1q f a36 36 c b v - yy 730 710 670 35 x18 r1q g a36 18 c b v - yy 780 720 36 x36 r1q g a36 36 c b v - yy 830 770 38 x18 r1q h a36 18 c b v - yy 780 720 39 x36 r1q h a36 36 c b v - yy 860 790 41 x18 r1q j a36 18 c b v - yy 630 590 42 x36 r1q j a36 36 c b v - yy 670 630 44 x18 r1q k a36 18 c b v - yy 780 720 45 x36 r1q k a36 36 c b v - yy 830 770 47 x18 r1q l a36 18 c b v - yy 780 720 48 x36 r1q l a36 36 c b v - yy 860 790 50 x18 r1q m a36 18 c b v - yy 630 590 51 x36 r1q m a36 36 c b v - yy 670 630 qdr ii+ / ddr ii+ qdr ii / ddr ii frequency (max) (mhz) cycle time (min) (ns) no yes no odt part number organi- zation 2.5 2.5 b2 yes b4 b2 ddrii+ b4 qdrii+ qdrii+ b4 2.0 ddrii+ b2 b4 2.0 b4 ddrii+ qdrii+ b4 ddrii+ b2 b4 qdrii+ b4 no product type burst length latency (cycle) r10ds0159ej0009
page : 20 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series common leakage currents & output voltage 8, 9 |i oh | d 0.1 ma v v ddq v ddq 0.2 v oh (low) output high voltage 8, 9 note 6 v v ddq /2 0.12 v ddq /2 0.12 v oh v ddq /2 0.12 0.2 5 2 max v v p a p a unit notes: 1. all inputs (except zq, v ref ) are held at either v ih or v il . 2. i out = 0 ma. v dd = v dd max, t khkh = t khkh min. 3. operating supply currents (i dd ) are measured at 100% bus utilization. i dd of qdr family is current of device with 100% write and 100% read cycle. i dd of ddr family is current of device with 100% write cycle (if i dd (write) > i dd (read)) or 100% read cycle (if i dd (write) < i dd (read)). 4. all address / data inputs are static at either v in > v ih or v in < v il . 5. reference value. (condition = nop currents are valid when entering nop after all pending read and write cycles are completed. ) 6. outputs are impedance-controlled. |i oh | = (v ddq /2)/(rq/5) for values of 175 :d rq d 350 : . 7. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) for values of 175 :d rq d 350 : . 8. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 9. hstl outputs meet jedec hstl class i and class ii standards. 10. 0 d v in d v ddq for all input balls (except v ref , zq, tck, tms, tdi ball). if r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series, balls with odt do not follow this spec. 11. 0 d v out d v ddq (except tdo ball), output disabled. note 7 i ol d 0.1 ma test condition 11 5 i lo output leakage current 8, 9 v ss v ol (low) output low voltage 8, 9 v ddq /2 0.12 v ol 10 2 i li input leakage current notes min symbol parameter r10ds0159ej0009
page : 21 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series common ac test conditions input waveform (rise/fall time d 0.3 ns) 1.25v 0.25v 0.75v 0.75v test points output waveform v ddq /2 test points v ddq /2 pf pf pf unit capacitance (ta = +25 q c, frequency = 1.0mhz, v dd =1.8v, v ddq =1.5v) 5 4 4 typ 6 5 5 max notes: 1. these parameters are sampled and not 100% tested. 2. except jtag (tck, tms, tdi, tdo) pins. v i/o = 0 v v clk = 0 v v in = 0 v test condition 1, 2 c clk clock input capacitance (k, /k, c, /c) 1, 2 c i/o output capacitance (q (separate) , dq (common) , cq, /cq) 1, 2 c in input capacitance (sa, /r, /w, /bw, d (separate) ) notes min symbol parameter -4.4 11.0 typ eia/jedec jesd51 test condition q c/w unit thermal resistance 1 m/s airflow notes: 1. these parameters are calculated under the condition. these are reference values. 2. tj = ta + ? ja ? pd tj = tc + ? jc ? pd where tj : junction temperature when the device has achieved a steady-state after application of pd ( r c) ta : ambient temperature ( r c) tc : temperature of external surface of the package or case ( r c) ? ja : thermal resistance from junction-to-ambient ( r c/w) ? jc : thermal resistance from junction-to-case (package) ( r c/w) pd : power dissipation that produced change in junction temperature (w) (cf.jesd51-2a) ? jc junction to case 1 ? ja junction to ambient notes symbol parameter r10ds0159ej0009
page : 22 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series common v v unit ac operating conditions typ v ref ? 0.2 max notes: 1. all voltages referenced to v ss (gnd). during normal operation, v ddq must not exceed v dd . 2. these conditions are for ac functions only, not for ac parameter test. 3. overshoot: v ih (ac) d v ddq + 0.5 v for t d t khkh /2 undershoot: v il (ac) t 0.5 v for t d t khkh /2 control input signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 4. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through the target ac level, v il (ac) or v ih (ac) . b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) . 1, 2, 3, 4 v il (ac) input low voltage 1, 2, 3, 4 v ref + 0.2 v ih (ac) input high voltage notes min symbol parameter output load conditions output load and voltage conditions 50 : zq q v ref 250 : z 0 = 50 : sram v ddq / 2 = 0.75v v ddq / 2 = 0.75v v dd v ddq v ss 1.8v r 0.1v 1.5v r10ds0159ej0009
page : 23 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins=00000.0111.0111.0000.0000 -- - 00000.0111.0111.0000.0000 --- 00000.0000.0000.0000.0000---rl=2.5 cq high to qvld valid k, /k high to output low-z k, /k high to output high-z cq, /cq high to output hold cq, /cq high to output valid k, /k high to echo clock hold k, /k high to echo clock valid k, /k high to output hold k, /k high to output valid output times k static to dll/pll reset lock time (k) clock phase jitter (k, /k) dll/pll timing /clock to clock (/k to k) clock to /clock (k to /k) clock low time (k, /k) clock high time (k, /k) average clock cycle time (k, /k) clock parameter ac characteristics ( read latency = 2.5 cycle ) (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series) (ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v, v ddq = 1.5v, v ref = 0.75v) t qvld t chqx1 t chqz t cqhqx t cqhqv t chcqx t chcqv t chqx t chqv t kc reset t kc lock t kc var t /khkh t kh/kh t klkh t khkl t khkh symbol 0.15 0.45 0.15 0.45 0.45 30 20 0.425 0.425 0.40 0.40 1.875 min -19 0.15 0.45 0.15 0.45 0.45 0.15 4.00 max 0.15 0.45 0.15 0.45 0.45 30 20 0.425 0.425 0.40 0.40 2.00 min -20 0.15 0.45 0.15 0.45 0.45 0.15 4.00 max 0.15 0.45 0.15 0.45 0.45 30 20 0.425 0.425 0.40 0.40 2.22 min -22 0.15 0.45 0.15 0.45 0.45 0.15 4.00 max 0.20 0.45 0.20 0.45 0.45 30 20 0.425 0.425 0.40 0.40 2.50 min -25 0.20 0.45 0.20 0.45 0.45 0.20 4.00 max 0.20 0.45 0.20 0.45 0.45 30 20 0.425 0.425 0.40 0.40 2.66 min -27 0.20 0.45 0.20 0.45 0.45 0.20 4.00 max 0.20 0.45 0.20 0.45 0.45 30 20 0.425 0.425 0.40 0.40 3.00 min -30 0.20 0.45 0.20 0.45 0.45 0.20 4.00 max ns ns ns ns ns ns ns ns ns ns us ns cy- cle cy- cle cy- cle cy- cle ns unit 7 5 5, 6 4, 7 4, 7 7 2 3 notes r10ds0159ej0009
page : 24 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 00000.0111.0111.0000.0000 -- - 00000.0111.0111.0000.0000--- 00000.0000.0000.0000.0000---rl=2.5 notes: 1. this is a synchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. v dd and v ddq slew rate must be less than 0.1 v dc per 50 ns for dll/pll lock retention. dll/pll lock time begins once v dd , v ddq and input clock are stable. it is recommended that the device is kept inactive during these cycles. this specification meets the qdr common spec. of 20 us. 3. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. echo clock is very tightly controlled to data valid / data hold. by design, there is a r 0.1 ns variation from echo clock to data. the datasheet parameters reflect tester guardbands and test setup variations. 5. transitions are measured r 100 mv from steady-state voltage. 6. at any given voltage and temperature t chqz is less than t chqx1 and t chqv . 7. these parameters are sampled. 8. t avkh , t ivkh , t khax , t khix spec is determined by the actual frequency regardless of part number (marking name). the following is the spec for the actual frequency. 0.30 ns for 7 533mhz & >500mhz 0.33 ns for 7 500mhz & >450mhz 0.40 ns for 7 450mhz & 8 250mhz 9. t dvkh , t khdx spec is determined by the actual frequency regardless of part number (marking name). the following is the spec for the actual frequency. 0.20 ns for 7 533mhz & >500mhz 0.22 ns for 7 500mhz & >450mhz 0.25 ns for 7 450mhz & >400mhz 0.28 ns for 7 400mhz & 8 250mhz remarks: 1. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 2. control input signals may not be operated with pulse widths less than t khkl (min). 3. v ddq is +1.5 v dc. v ref is +0.75 v dc. 4. control signals are /r, /w (qdr series), /ld, r-/w (ddr series), /bw, /bw0, /bw1, /bw2 and /bw3. setup and hold times of /bwx signals must be the same as those of data-in signals. k, /k rising edge to data-in hold k rising edge to control inputs hold k rising edge to address hold hold times data-in valid to k, /k rising edge control inputs valid to k rising edge address valid to k rising edge setup times parameter t khdx t khix (qdrii+ b4 & ddrii+) t khix (qdrii+ b2) t khax (qdrii+ b4 & ddrii+) t khax (qdrii+ b2) t dvkh t ivkh (qdrii+ b4 & ddrii+) t ivkh (qdrii+ b2) t avkh (qdrii+ b4 & ddrii+) t avkh (qdrii+ b2) symbol 0.20 0.30 0.30 0.20 0.30 0.30 min -19 max 0.22 0.33 0.33 0.22 0.33 0.33 min -20 max 0.25 0.40 0.40 0.25 0.40 0.40 min -22 max 0.28 0.40 0.40 0.28 0.40 0.40 min -25 max 0.28 0.40 0.40 0.28 0.40 0.40 min -27 max 0.28 0.40 0.40 0.28 0.40 0.40 min -30 max ns ns ns ns ns ns unit 1, 9 1, 8 1, 8 1, 9 1, 8 1, 8 notes r10ds0159ej0009
page : 25 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins=00000.0010.0010.0000.0000 -- - 00000.0010.0010.0000.0000 ---00000.0010.0010.0000.0000--- r1qb_rl=2.5 r tqvld -tqvld tqvld -tqvld 1 2 3 4 5 6 7 8 9 10 11 12 13 k, /k nop read (burst of 2) read (burst of 2) write (burst of 2) nop nop tkhax tavkh /ld:r-/w sa tkhkh tkhkl tklkh tkh/kh t/khkh k /k tkhix tivkh write (burst of 2) read (burst of 2) a0 00 00 01 01 1x 1x 1x a2 a6 a4 notes: 1. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, etc. 2. outputs are disabled (high-z) n clock cycle after the last read cycle. here, n = read latency + burst length u 0.5. 3. in this example, if address a8 = a7, then data q80 = d70, q81 = d71, etc. write data is forwarded immediately as read results . 4. to control read and write operations, /bw signals must operate at the same timing as data-in signals . 5. the third nop cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to p revent bus contention. read (burst of 2) read (burst of 2) write (burst of 2) write (burst of 2) 01 01 00 00 01 a1 a3 a5 a8 a7 tchcqv -tchcqx tchcqv -tchcqx q00 qx1 q01 q10 q11 q20 q21 q30 tchqv -tchqx tchqv -tchqx tcqhqv -tcqhqx -tchqx1 q31 tchqz qx0 qx1 dq cq /cq qvld d40 d41 d50 d51 d60 d61 d70 d71 tkhdx tdvkh tkhdx tdvkh nop timing waveforms (ddrii+, b2, read latency = 2.5 cycle) r10ds0159ej0009
page : 26 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series jtag specification these products support a limited set of jtag functions as in iee e standard 1149.1. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are internally pulled up and may be unconnected, or may be connected to vdd through a pull up resistor. tdo should be left unconnected. 1r 11r 10r 2r pin assignments test mode select. this is the command input for the tap controller state machine. tms test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdi test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. tdo test access port (tap) pins notes: the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the tap controller state is also reset on sram power-up. notes test clock input. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tck description symbol i/o common r10ds0159ej0009
page : 27 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series 0 v d v in d v dd , output disabled p a 5.0 5.0 i lo output leakage current i olc = 100 p a v 0.2 v ol1 output low voltage i olt = 2 ma v 0.4 v ol2 5.0 0.5 v dd + 0.3 max v 0.3 v il input low voltage 0 v d v in d v dd p a 5.0 i li input leakage current |i ohc | = 100 p a v 1.6 v oh1 output high voltage |i oht | = 2 ma v 1.4 v oh2 tap dc operating characteristics (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series) (ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v) typ v unit notes: 1. all voltages referenced to v ss (gnd). 2. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . notes +1.3 v ih input high voltage min symbol parameter common r10ds0159ej0009
page : 28 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series v 0.9 v ref input timing measurement reference levels notes v v ns v unit 0.9 output timing measurement reference levels 0.9 test load termination supply voltage (v tt ) 0 to 1.8 v il , v ih input pulse levels d 1.0 tr, tf input rise/fall time see figures output load tap ac test conditions conditions symbol parameter common external load at test 50 : v tt = 0.9v tdo z 0 = 50 : dut 20pf 1.8v input waveform 0v 0.9v 0.9v test points output waveform 0.9v test points 0.9v output load condition r10ds0159ej0009
page : 29 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series ns 5 t thmx tms hold 1 ns 5 t cs capture setup 1 ns 5 t ch capture hold ns 5 t dvth tdi valid to tck high ns 5 t thdx tck high to tdi invalid ns 0 t tlqx tck low to tdo unknown 10 max ns 20 t thtl tck high pulse width ns 20 t tlth tck low pulse width ns 5 t mvth test mode select (tms) setup ns t tlqv tck low to tdo valid tap ac operating characteristics (ta = 0 ~ +70 q c @ r1q*a*****bg-** r ** series) (ta = -40 ~ +85 q c @ r1q*a*****bg-** i ** series) (v dd =1.8v r 0.1v) typ ns unit notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. notes 50 t thth test clock (tck) cycle time min symbol parameter common r10ds0159ej0009
page : 30 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series notes bs [109:1] 109 bits boundary scan register bp 1 bit bypass register id [31:0] 32 bits id register test access port registers ir [2:0] symbol 3 bits instruction register length register name tap controller timing diagram tck tdi tms tdo pi (sram) tthtl tthth ttlth tmvth tthmx tdvth tthdx tcs tch ttlqv ttlqx common r10ds0159ej0009
page : 31 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series 3, 5 when the sample instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo balls. sample (/preload) 0 0 1 - reserved 1 0 1 - reserved 0 1 1 the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. bypass 1 1 1 the reserved instructions are not implemented but are reserved for future use. do not use these instructions. if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z), moving the tap controller into the capture-dr state loads the data in the rams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo balls in shift- dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. the extest instruction allows circuitry external to the component package to be tested. boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. description idcode 1 0 0 3, 4, 5 sample-z 0 1 0 reserved 1 1 0 tap controller instruction set extest instruction notes: 1. data in output register is not guaranteed if extest instruction is loaded. 2. after performing extest, power-up conditions are required in order to return part to normal operation. 3. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. 4. clock recovery initialization cycles are required after boundary scan. 5. for r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series, odt is disabled in extest, sample-z or sample mode. 1, 2, 3, 5 notes 0 0 0 ir0 ir1 ir2 common r10ds0159ej0009
page : 32 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit # boundary scan order 11e 10f 9f 11g 11f 9g 10g 11h 11j 10j 9k 9j 10k 11k 10l 9l 11m 11l 9n 9m 11n 10m 9p 10n 10p 11p 9r 8p 8r 7r 7n 7p 6n 6p 6r ball id dq3 nc nc nc nc nc nc zq nc dq2 nc nc nc nc nc nc nc dq1 nc nc nc nc nc nc nc dq0 sa sa sa sa sa sa sa c or qvld /c or nc or odt x9 signal names dq6 nc nc nc dq5 nc nc zq nc dq4 nc nc nc dq3 nc nc nc dq2 nc nc nc dq1 nc nc nc dq0 sa sa sa sa sa sa sa c or qvld /c or nc or odt x18 dq6 nc nc dq14 dq5 nc nc zq dq4 dq13 nc nc dq12 dq3 nc nc dq1 dq2 nc nc dq10 dq11 nc nc dq9 dq0 sa sa sa sa sa sa sa c or qvld /c or nc or odt x36 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 bit # 3d 1b 1c 3b 2b 1a 2a 3a 4b 5c 4a 5a 5b 6a 6b 7b 7a 8a 6c 7c 8b 9a 10a 11a 10b 9b 11c 11b 9d 9c 11d 10c 9e 10d 10e ball id nc nc nc nc nc /cq nc sa sa sa r-/w nc nc /k k /bw nc /ld sa sa sa sa sa cq nc nc nc dq4 nc nc nc nc nc nc nc x9 signal names dq10 nc nc nc dq9 /cq nc sa sa sa r-/w /bw1 nc /k k /bw0 nc /ld sa0 or nc sa sa sa sa cq nc nc nc dq8 nc nc nc dq7 nc nc nc x18 dq19 nc nc dq18 dq27 /cq nc sa sa sa r-/w /bw2 /bw3 /k k /bw0 /bw1 /ld sa0 or nc sa sa sa nc cq nc nc dq7 dq8 nc nc dq16 dq17 nc nc dq15 x36 r10ds0159ej0009
page : 33 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series notes: in boundary scan mode, 1. clock balls (k, /k, c, /c) are referenced to each other and must be at opposite logic levels for reliable operation. 2. cq and /cq data are synchronized to the respective c and /c (except extest, sample-z). 3. if c and /c tied high, cq is generated with respect to k and /cq is generated with respect to /k (except extest, sample-z). 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 bit # boundary scan order 1k 2k 3j 3k 2j 1j 1h 2g 3g 1f 1g 3f 2f 1e 2e 2d 3e 2c 1d 3c ball id nc nc nc nc nc nc /doff nc dq6 nc nc nc nc nc nc nc dq5 nc nc nc x9 signal names nc nc nc dq14 nc nc /doff nc dq13 nc nc nc dq12 nc nc nc dq11 nc nc nc x18 nc nc dq32 dq23 nc nc /doff dq31 dq22 nc nc dq21 dq30 nc nc dq29 dq20 nc nc dq28 x36 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 bit # 5r 5n 5p 4p 4r 3r 1p 2p 2n 3p 2m 1n 3m 3n 1l 1m 3l 2l ball id inter- nal sa sa sa sa sa sa nc nc nc dq8 nc nc nc nc nc nc nc dq7 x9 signal names inter- nal sa sa sa sa sa sa nc nc nc dq17 nc nc nc dq16 nc nc nc dq15 x18 inter- nal sa sa sa sa sa sa nc nc dq35 dq26 nc nc dq34 dq25 nc nc dq24 dq33 x36 r10ds0159ej0009
page : 34 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series tap controller state diagram notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck. select ir scan capture ir shift ir exit1 ir pause ir exit2 ir update ir 0 0 1 0 1 1 0 1 0 0 1 select dr scan capture dr shift dr exit1 dr pause dr exit2 dr update dr 0 0 1 0 1 1 0 1 0 0 1 run test/idle 0 10 1 test logic reset 1 1 0 0 11 common id register ># ># # 313029282726252423222120191817161514131211109876543210 symbol rrr0cmmmaww01qqqbos0010001000111 rrr q 000 0 001 1 010 q 011 0 1 cq 00 11 mmm b 010 0 011 1 101 o 110 0 a1 0s 10 ww 1 00 10 11 :: density = 72mb density = 36mb latency=1.5 (@ii), latency=2.0 (@ii+) latency=2.5 (@ii+) burst length = 2 word burst revis on 0 ii (q dr-ii, ddr-ii) revison 1 revison 2 revison 3 start bit (0) g - revision number (31 :29) type number (28 : 12) x36 36m&72m w/o odt, 144m,288m 36m&72m w/ odt 144m&288m w/o odt, 36m,72m 144m&288m w/ odt burst length = 4 word burst density = 144mb density = 288mb common i/o separate i/o vendor jedec code x18 x9 (11 : 1) ii+ (q dr-ii+, ddr-ii+) ddr qdr with odt without odt r10ds0159ej0009
page : 35 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series package dimensions and marking information both pb parts and pb-free parts are available. hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m 0.6 g mass (typ.) 165fhe previous code plbg0165fd-a p-lbga165-15x17-1.00 renesas code jeita package code max nom min - 1.5 - z e - 2.5 - z d 0.15 - - y 0.55 0.5 0.45 b - 1.0 - [e] 0.37 0.32 0.27 a1 1.4 - - a 17.1 17.0 16.9 e 15.1 15.0 14.9 d 0.2 - - x dimension in mm reference symbol s y - ab s ?x(m) - top view side view bottom view marking information 1st row : vender name (r enesas ) 2nd row: part number 3rd row : y : year code ww : week code xxxx : renesas internal use 4th row : country name (japan) + "none" --- pb -free parts + "pb-f" --- pb-free parts s a1 a z e z d abcdefghjklmnpr 1 2 3 4 5 6 7 8 9 10 11 [e] [e] ?b index mark a d index mark (laser mark) b e r1qaa7236abg-20r ywwxxxx japan pb-f this part number or mark is just one example. r10ds0159ej0009
page : 36 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m revision history description date rev. revision history (1) 4gx &cvg %qoogpv 4gxc +pkvkcnkuuwg 4gxd %qttgevgfv[rqukp&%%jctcevgtkuvkeu81* 81.8&&3dd 4gxe #ffgf5rggf$kp6cdng #ffgf1&6vkokpiejctvvq3&4++ cpf&&4++ ugtkgu %qttgevgfv[rqukp)gpgtcn&guetkrvkqp1&6rkp3?3p& ?&p 7rfcvgf4geqoogpfgf&%1rgtcvkpi%qpfkvkqpu8tgh?8 ? 8
++ ugtkgu #ffgfeqoogpvvq6jgtocn4gukuvcpegugevkqp6jgugctgtghgt gpegxcnwgu 4gxg #ffgf)gpgtcvkqp0wodgt6cdng %jcpigf/ctmkpi0cogkp2ctv0wodgt&ghkpkvkqp6cdng #ffgfoctmkpikphqtocvkqpvq2cemcig&kogpukqp+phqtocvkqpu gevkqp %qttgevgf1&61p1hhvkokpikp1&6rkpvcdng 7rfcvgfokpkowohtgswgpe[qh3&4++ cpf&&4++ ugtkgu %jcpigfrkppcogkp2kp#ttcpigogpvqh&&4++ ugtkgu5#5# 0% #ffgfvjgtqyvq-6twvj6cdng4.cpf4. 7rfcvgf5'672e[engu++ ugtkgu&..nqemvkogwu e[eng #ffgfeqoogpvvq1&6qpqhh6kokpi%jctvugevkqp1&6qpqhh uykvejkpi vkokpiuctggfigcnkipgfykvj%3qt%3 7rfcvgf6jgtocn4gukuvcpeg 4gxj #ffgfurggfdkpvq3&4++$zzu gtkgu 7rfcvgf2cemcig&kogpukqpu/cuui#
oczoo 7rfcvgf1rgtcvkpi5vcpfd[5wrrn[%wttgpvu #ffgfeqoogpvvq2qygtwrcpf+pkvkcnk\cvkqp5gswgpegugevkqp #rrn[8tgh chvgt8ffsqtcvvjgucogvkogcu8ffs 7rfcvgf5rggf$kp6cdng #ffgf4gpgucu3&454#/*qogrcig74.vqpqvguqhhtqpvrcig 7rfcvgf2qygtwrcpf+pkvkcnk\cvkqp5gswgpeg 7rfcvgf&..%qpuvtckpvu 7rfcvgf1rgtcvkpi5wrrn[%wttgpvcpf5vcpfd[5wrrn[%wttgpv 7rfcvgf6jgtocn4gukuvcpeg %jcpigftgoctmuqh#%%jctcevgtkuvkeuqp%qpvtqnukipcnu %jcpigfeqorcp[pcog4'0'5#5nqiqcpfdcugeqnqthtqovjqugqh 4gpgucu 6gejpqnqi[vq4gpgucu'ngevtqpkeu %jcpigfxgpfgtpcogoctmkpikp2cemcig&kogpukqpucpf/ctmkpi +phqtocvkqp ugevkqp #ffgf#igpgtcvkqpvq/ugtkgu %jcpigfvjgrkpfguetkrvkqphqt0%rkp %jcpigfpqvgqh6#2%qpvtqnngt+puvtwevkqp5gv%nqemtgeq xgt[ kpkvkcnk\cvkqpe[enguctgtgswktgfchvgtdqwpfct[uecp %jcpigf8ffstcpigqh++ ugtkgu8ffsd88?8ff #ffgf0qvgcpf0qvgvq#%%jctcevgtkuvkeuvcdnghqt++ ug tkgu 7rfcvgf5rggf$kp6cdnghqt/ #ffgf0qvgvq)gpgtcvkqp0wodgt6cdng 7rfcvgf5rggf$kp6cdnghqt/cpf/ 4gxe 7rfcvgf1rgtcvkpi5wrrn[%wttgpvcpf5vcpfd[5wrrn[%wttgpv6cd nghqt/ cpf/ 4gxc %jcpigf+pkvkcnk\cvkqp5gswgpeg+pkvkcne[engqh++ ugtkgu e[engu wu 4gxc #ffgf0qvgvq#%%jctcevgtkuvkeuvcdnghqt ++ugtkgu 7rfcvgf#%%jctcevgtkuvkeuhqtvjgugtkguqh4. 7rfcvgf5rggf$kp6cdnghqt/// #ffgf430#432#ugtkguvq/3&4nkpgwr %jcpigf,6#)+&4gikuvgt
+&%qfg //yq1&6// //y1&6 //yq1&6// //y1&6

/
/ 4gxc 4gxd 4gxd 4gxc 4gxc 4gxf 4gx 4gxc 4gxi 4gxk 4gxc r10ds0159ej0009
page : 37 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m revision history (2) 4gx &cvg %qoogpv #ffgf0qvgvqv38.&kp#%%jctcevgtkuvkeuvcdnghqt++ ugtk gu %jcpigffguetkrvkqpqhv38.&kp#%%jctcevgtkuvkeuvcdnghqt4. ugtkgu %3jkijvq38.&xcnkf%3jkijvq38.&xcnkf 7rfcvgf4goctmuqh#%%jctcevgtkuvkeuvcdng 7rfcvgfv-*-*
oczkp#%%jctcevgtkuvkeuvcdnghqt3&4++ $u gtkgu #ffgfzoorcemcignkpgwrvq/++ /++++ ugtkgu 7rfcvgf2cemcig&kogpukqpuhqtzoorcemcig 7rfcvgf6jgtocn4gukuvcpeghqtzoorcemcig %jcpigf6kvng1tfgtkpi+phqtockqp2ctv0wodgt&ghkpkvkqp t5rggf $kp6cdng4gpgucu/3&4&&454#/.kpgwr 4gxc 7rfcvgf5rgekhkecvkqphqt1&61rvkqp 4gxd 4gxc r10ds0159ej0009
page : 38 rev. 0.09a : 2011.09.14 r1qba36**cb* / r1qea36**cb* series ? 2011 renesas electronics corporation. all rights reserved. renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan, r.o.c. tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 renesas sales offices http://www.renesas.com --- refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics corporation headquarters: nippon bldg., 2-6-2, ote-machi, chiyoda-ku, tokyo 100-0004, japan notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the us e of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circu it examples, is current as of the date this document is issued. such information, however,is subject to change without any prior notice. before purch asing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, pleas e pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whats oever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the tota l system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaran ties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the applicat ion and use of the information in this document or renesas products. 7. the products described in this document are intended for usage in general electronics applications (computer, personal equipm ent, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). the products are not designed, manufactured, t ested or warranted for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and tr affic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. unintended usage of the pr oducts shall be made at the customer?s own risk. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesa s products in any of the foregoing applications shall indemnify and hold harmless renesas electronics corp., its affiliated companies and their of ficers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum ra ting, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characterist ics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to gua rd against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as sa fety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evalu ate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or a ffixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas pr oducts may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from ren esas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. common

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